1. Field of the Invention
The present invention applies to class-D amplifiers, and in particular, class-D audio amplifiers operating in a purely digital signal environment and, therefore, suitable for integration as part of a system on a chip.
2. Description of the Related Art
Referring to FIG. 1, as is well known in the art, class-D amplifiers receive an analog input signal 1 (e.g., depicted as a pure sine wave) and generates a digital output signal 3 (e.g., a bipolar, or three-level, pulse width modulated signal) having a low frequency component that is proportional to the input signal 1. As is well known, one advantage of a class-D amplifier over a linear amplifier (e.g., class-AB) is greater efficiency, often approaching 100%. One common application for a class-D amplifier is as a driver for a loudspeaker. Such high efficiency makes class-D audio amplifiers quite suitable for integration as part of a system on a chip. One example of such a system on a chip would be a baseband processor for cellular or cordless telephones.
Referring to FIG. 2, a class-D amplifier 4 has often been implemented using a signal comparison circuit 6, a reference signal source 8, a non-inverting output driver 10a and an inverting output driver 10b interconnected substantially as shown. The analog input signal 1 is compared against a triangular reference signal 9 produced by the reference signal source 8. The resultant comparison signal 7 is buffered by the output driver amplifiers 10a, 10b to produce the drive signals 11a, 11b for the loudspeaker 12. Usually, a low pass filter (not shown) is also placed between the output signal 11 and loudspeaker 12.
This amplifier 4 can be implemented using only a few simple analog circuit blocks. However, such a circuit 4 requires a stable power supply voltage VDD for the output buffer amplifiers 10a, 10b. Accordingly, since there is no feedback from the actual digital output signals 11a, 11b any variations in the power supply voltage VDD will be reflected in the output signals 11a, 11b. Hence, such a circuit 4 has a poor power supply rejection ratio (PSRR). Further, since the output signal switching frequency is not very high, the external low pass filter (not shown) is usually necessary.
Referring to FIG. 3, a higher PSRR can be achieved with a class-D amplifier circuit 14 in which a linear class-AB amplifier 16 is used. Such a circuit 14 includes the class-AB amplifier 16, a current sensing circuit 18 (e.g., an electronic equivalent of an ammeter) and a digital output amplifier 20, interconnected substantially as shown. The analog input signal 1 is buffered by the differential class-AB amplifier circuit 16 operating as a voltage follower circuit. The amplified input signal 17 passes through the current sensing circuitry 18, the main output signal 19a of which provides the feedback for the class-AB amplifier 16 and some amount of drive for the loudspeaker 12.
The current sensing output 19b of the current sensing circuitry 18 drives the digital output amplifier 20. It is this output 21 of the digital output buffer amplifier 20 that provides the majority of the drive current for the loudspeaker 12. Hence, the output 19a from the class-AB amplifier circuit 16 need only provide that relatively small amount of current necessary for maintaining the signal to the loudspeaker 12 at the desired level. A low pass filter, such as an inductor 22, is necessary to provide isolation between the output terminals of the class-AB 16 and output 20 amplifiers.
While this circuit 14 provides an improved PSRR, it nonetheless continues to require an external low pass filter 22, as well as an analog input signal 1. Accordingly, implementation of this type of circuitry 14 in fully integrated form (e.g., for use as part of a system on a chip) remains problematic.
Referring to FIG. 4, another conventional class-D amplifier circuit 30 uses a delta-sigma modulator (analog) 32, a signal slicer 34 and output buffer amplifiers 36a, 36b, interconnected substantially as shown, to drive the loudspeaker 12. A differential analog input signal 31 is processed by the delta-sigma modulator 32 to produce a three-level output signal 33 (having values of xe2x88x921, 0 or +1). This signal 33 is processed by the signal slicer 34 to produce the drive signals 35a, 35b for the output buffer amplifiers 36a, 36b. These output signals 35a, 35b are binary in that they have one of two states, depending upon the value of the slicer input signal 33. For example, as indicated in FIG. 4, if the slicer input signal 33 has a value of +1, the Out+ signal 37a equals the positive power supply voltage VDD, and the Outxe2x88x92 signal 37b equals the potential of the negative power supply voltage terminal VSS. The output drive signals 37a, 37b also serve as the feedback signals for the delta-sigma modulator 32 (in accordance with well known delta-sigma modulator circuit principles).
This type of circuit 30 has a good PSRR since the output buffer amplifiers 36a, 36b form part of the feedback loops for the delta-sigma modulator 32. Accordingly, variations in the power supply voltage VDD or other voltage drops in the output amplifiers 36a, 36b are compensated by virtue of the feedback loops. Additionally, no external low pass filtering is required when a high oversampling ratio (OSR) is used in combination with the three-level output signal 33 generated by the delta-sigma modulator. However, the delta-sigma modulator 32 must still function as an analog circuit in order to compensate for analog variations in the power supply voltage VDD and other voltage drops in the output amplifiers 36a, 36b. 
Accordingly, it would be desirable to have a class-D amplifier circuit with a very high PSRR, no requirement for external filtering, and the capability for operating with a digital input signal.
In accordance with the presently claimed invention, a class-D amplifier is provided with a high power supply rejection ratio (PSRR) while accepting a digital input signal and not requiring an output signal filter, thereby being ideally suited for integration as part of a system on a chip. The input signal is converted by a first delta-sigma modulator to provide a first multivalue digital signal representing the desired output. This first multivalue digital signal is combined with a second multivalue digital signal provided by a second delta-sigma modulator to provide a third multivalue digital signal. This third multivalue digital signal is converted to binary digital output signals for differentially driving a load. These binary digital output signals are also fed back and combined with the first multivalue digital signal to provide the feedback signal for the second delta-sigma modulator.
In accordance with one embodiment of the presently claimed invention, a class-D amplifier includes delta-sigma modulation circuitry, signal combining circuitry and signal conversion circuitry. The delta-sigma modulation circuitry receives and converts a digital input signal to a first multivalue digital signal corresponding to the digital input signal, and receives a feedback signal and in response thereto receives and converts an analog input signal to a second multivalue digital signal corresponding to the feedback signal. First signal combining circuitry, coupled to the delta-sigma modulation circuitry, receives and combines the first and second multivalue digital signals and in response thereto provides a third multivalue digital signal corresponding to a sum of the first and second multivalue digital signals. The signal conversion circuitry, coupled to the first signal combining circuitry, receives and converts the third multivalue digital signal to first and second binary digital signals with first and second binary signal values that vary in relation to the third multivalue digital signal. Second signal combining circuitry, coupled to the delta-sigma modulation circuitry and the signal conversion circuitry, receives and combines the first multivalue digital signal and the first and second binary digital signals and in response thereto provides the feedback signal.
In accordance with another embodiment of the presently claimed invention, a class-D amplifier includes modulator means, combiner means and converter means. The modulator means is for receiving and converting a digital input signal to a first multivalue digital signal corresponding to the digital input signal, and receiving a feedback signal and in response thereto receiving and converting an analog input signal to a second multivalue digital signal corresponding to the feedback signal. First combiner means is for combining the first and second multivalue digital signals and providing a third multivalue digital signal corresponding to a sum of the first and second multivalue digital signals. The converter means is for converting the third multivalue digital signal to first and second binary digital signals with first and second binary signal values that vary in relation to the third multivalue digital signal. Second combiner means is for combining the first multivalue digital signal and the first and second binary digital signals and providing the feedback signal.
In accordance with still another embodiment of the presently claimed invention, a method for class-D signal amplification includes:
performing delta-sigma modulation of a digital input signal to generate a first multivalue digital signal corresponding to the digital input signal;
receiving a feedback signal and in response thereto performing delta-sigma modulation of an analog input signal to generate a second multivalue digital signal corresponding to the feedback signal;
combining the first and second multivalue digital signals to generate a third multivalue digital signal corresponding to a sum of the first and second multivalue digital signals;
converting the third multivalue digital signal to first and second binary digital signals with first and second binary signal values that vary in relation to the third multivalue digital signal; and
combining the first multivalue digital signal and the first and second binary digital signals to generate the feedback signal.